The frequency of a clock signal used in data transfer between a memory and a CPU (Central Processing Unit) increases year by year. For this reason, it has become more difficult to realize high-quality data transfer in a high frequency operation.
Meanwhile, various specifications and operation modes are considered in order to improve bus efficiency. However, an obstacle thereof is a refresh operation. A frequency of the refresh operation tends to increase in accordance with increase of a memory capacity and development of a fine process, and accordingly it becomes important to suppress lowering of the bus efficiency caused by the refresh operation.
As a high-speed operating DRAM (Dynamic Random Access Memory) operating in synchronization with a clock signal, an SDRAM (Synchronous Dynamic Random Access Memory) and a GDDR (Graphics Double Data Rate) are generally known. To carry out a read operation and a write operation, at first, an “IDLE” state is transited to an “ACTIVE” state in response to an active command and a row address. When a read command or a write command and a column address are further supplied in this state, a sequential read operation or write operation can be performed by a multi-bank accessing operation. The high bus efficiency can be retained in this state.
Meanwhile, in a pseudo SRAM which does not have an auto-refresh command, since the refresh operation is hidden in a latency of the read or write, the lowering of the bus efficiency caused by the refresh operation can be eliminated.
A semiconductor memory device described in Patent Literature 1 has a plurality of banks including memory cell arrays where dynamic type memory cells (the pseudo SRAM) are arranged in a matrix. The semiconductor memory device includes an address counter for outputting a series of addresses including an address supplied from outside as a first address in sequence for every period of a clock signal from the outside; an access control circuit for executing a read access, a write access, and a refreshing access; and a refreshing access control circuit for controlling the access control circuit to execute the refreshing access. An outputted address from the address counter is set as a row address used for selecting a word line in the memory cell array, a column address used for selecting a bit line in the memory cell array, and a bank address used for selecting the bank. In a burst operation, the read access or the write access is continuously executed in accordance with the series of addresses to the plurality of memory cells existing over the plurality of banks. In this case, in a case of executing the read access, the refreshing access control circuit permits the access control circuit to execute the refreshing access to the bank to which the read access has been performed in accordance with timing at which a bank address is changed, after the access control circuit performed the read access to the bank corresponding to the changed bank address.
In a semiconductor memory device described in Patent Literature 2, a part of address terminals serves as a common terminal shared with a data terminal for outputting and/or inputting. A part or all of the remaining address terminals serve as an address-dedicated terminal for accessing in a page. In the semiconductor memory device, to a page selected based on an address from the common terminal, sequential outputting and/or inputting of plural pieces of data in a page is performed through the common terminal on the basis of an address signal inputted to the address-dedicated terminal.